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| SUMMIT MICROELECTRONICS, Inc. Preliminary SMS2916 3 and 5 Volt Systems Precision Voltage Supervisory Circuit With Watchdog Timer and 16K I2C Memory FEATURES * Precision Voltage Monitor - Automatic VCC Supply Monitor - Complementary reset outputs for complex microcontroller systems - Integrated memory write lockout function - No external components required * Watchdog Timer - Nominal 1.6 second Timeout * Memory Internally Organized 2K X 8 - Two Wire Serial Interface (I2CTM) * High Reliability - Endurance: 1,000,000 erase/write cycles - Data retention: 100 years * 8-Pin PDIP or SOIC Packages OVERVIEW The SMS2916 is a power supervisory circuit that monitors VCC (either in a 5V system or 3V system) and will generate complementary reset outputs. The reset pins also act as I/Os and may be used for signal conditioning. The SMS2916 also has an on-board watchdog timer that has a nominal time out period of 1.6 seconds. The SMS2916 integrates a 16K-bit nonvolatile serial memory. It features the industry standard I2C serial interface allowing quick implementation in an end-users' system. BLOCK DIAGRAM VCC 8 2 RESET 5KHz Oscillator RESET PULSE GENERATOR VCC + GND 4 1.26V VTRIP RESET CONTROL 7 RESET WATCHDOG TIMER SCL SDA 6 5 EEPROM MEMORY ARRAY WDI 1 2028 ILL2.1 SUMMIT MICROELECTRONICS, Inc. * 300 Orchard City Drive, Suite 131 * Campbell, CA 95008 * Telephone 408-378-6461 * Fax 408-378-6586 * www.summitmicro.com (c) SUMMIT MICROELECTRONICS, Inc. 1998 2028-02 4/24/98 Characteristics subject to change without notice 1 SMS2916 Preliminary PIN CONFIGURATIONS PIN NAMES Symbol WDI WDI RESET NC GND 1 2 3 4 8 7 6 5 VCC RESET SCL SDA 2028 ILL1.2 Pin 1 Description Watchdog Input /a high to low transition will clear the watchdog timer Active Low RESET Input/Output No Connect, tie to ground or leave open Analog and Digital Ground Serial Memory Input/ Output data line Serial Memory clock input Active High RESET Input/ Output Supply Voltage 2028 PGM T1.1 RESET NC GND SDA SCL RESET VCC 2 3 4 5 6 7 8 VCC = 3.0 0r 5.0 PB_RST ALE SMS2916 WDI Vcc 8051 Type MCU RST SCL (P0.0) SDA (P0.1 RESET RESET NC GND SCL SDA I 2C Peripheral RESET SCL SDA 2028 ILL3.1 FIGURE 1. TYPICAL APPLICATION USING DUAL RESET FUNCTION AND WATCHDOG TIMER 2028-02 4/24/98 2 SMS2916 Preliminary +5VDC RST SMS 2916 WDI Vcc RESET RESET Z80 I/O I/O NC SCL GND SDA FIGURE 2. TYPICAL APPLICATION CONFIGURATION USING SYSTEM DECODE LOGIC TO RESET WDI CAPACITANCE TA = 25C, f = 100KHz Symbol CIN LOUT Parameter Input Capacitance Output Capacitance Max 5 8 Units pF pF 2028 PGM T2..0 tR tF tH IGH tLOW tSU:STO SCL tSU:SDA tHD:SDA tHD:DAT tSU:DAT tBUF SDA In tDH tAA SDA Out 2028 ILL5.0 FIGURE 3. BUS TIMING Decoder 2028 ILL4.1 2028-02 4/24/98 3 SMS2916 Preliminary ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ............................................................................................................................... -40C to +85C Storage Temperature ..................................................................................................................................... -65C to +125C Soldering Temperature (less than 10 seconds) ................................................................................................................... 300C Supply Voltage ............................................................................................................................................................. 0 to 6.5V Voltage on Any Pin ....................................................................................................................................... -0.3V to VCC+0.3V ESD Voltage (JEDEC method) .......................................................................................................................................... 2,000V NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min 0C -40C Max +70C +85C 2028 PGM T3.0 DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol ICC ISB ILI ILO VIL VIH VOL Parameter Supply Current (CMOS) Standby Current (CMOS) Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Conditions SCL = CMOS Levels @ 100KHz SDA = Open All other inputs = GND or VCC SCL = SDA = VCC All other inputs = GND VIN = 0 To VCC VOUT = 0 To VCC S0, S1, S2, SCL, SDA, RESET S0, S1, S2, SCL, SDA, RESET IOL = 3mA SDA 0.7xVCC 0.4 VCC =5.5V VCC =3.3V VCC =5.5V VCC =3.3V Min Max 3 2 50 25 10 10 0.3xVCC Units mA mA A A A A V V V 2028 PGM T4.0 AC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol Parameter SCL Clock Frequency Clock Low Period Clock High Period Bus Free Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Clock to Output Data Out Hold Time SCL and SDA Rise Time SCL and SDA Fall Time Data In Setup Time Data In Hold Time Noise Spike Width @ SCL, SDA Inputs Write Cycle Time Noise Suppression Time Constant SCL Low to SDA Data Out Valid SCL Low to SDA Data Out Change Before New Transmission Conditions 2.7V to 4.5V Min 0 4.7 4.0 4.7 4.7 4.0 4.7 0.3 0.3 1000 300 250 0 100 10 3.5 Max 100 4.5V to 5.5V Min Max 400 1.3 0.6 1.3 0.6 0.6 0.6 0.2 0.2 300 300 100 0 100 10 0.9 Units KHz s s s s s s s s ns ns ns ns ns ms 2028 PGM T5.0 fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR 2028-02 4/24/98 4 SMS2916 Preliminary tGLITCH VTRIP VRVALID tRPD tPURST tPURST VCC RESET tRPD RESET 2028 ILL6.0 FIGURE 4. RESET OUTPUT TIMING RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS TA = -40C to +85C SMS2916-2.7 Symbol VTRIP tPURST tRPD VRVALID tGLITCH VOLRS VOHRS Reset Trip Point Power-Up Reset Timeout VTRIP to RESET Output Delay RESET Output Valid Glitch Reject Pulse Width RESET Output Low Voltage IOL= 1mA RESET Output High Voltage IOH = 800 A VCC-.75 1 30 0.4 Parameter Min 2.55 130 Max 2.7 270 5 SMS2916-A Min 4.25 130 Max 4.5 270 5 1 30 0.4 VCC-.75 SMS2916-B Min 4.5 130 Max 4.75 270 5 1 30 0.4 VCC-.75 Unit V ms s V ns V V 2028 PGM T6.0 2028-02 4/24/98 5 SMS2916 Preliminary PIN DESCRIPTIONS Serial Clock (SCL) - The SCL input is used to clock data into and out of the device. In the WRITE mode, data must remain stable while SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL. Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output and may be wireORed with any number of open-drain or open-collector outputs. RESET - RESET is an active low output. Whenever VCC is below VTRIP the SMS2916 will drive the RESET pin to ground. The RESET pin is an I/O and can be used as a reset input. Refer to Figure 1 as an example use of this pin as a push button switch debounce circuit. It should be noted this is an open drain output and an external pull-up resistor tied to VCC is needed for proper operation. RESET -- RESET is an active high output. Whenever VCC is below VTRIP the SMS2916 will drive the RESET pin to the VCC rail. The RESET pin is an I/O and can be used as a reset input. It should be noted this is an open drain output and an external pull-down resistor tied to ground is needed for proper operation. WDI - The WDI input is used as a hardware method of clearing the watchdog timer. A high to low transition on this pin will clear the watchdog timer. If a transition is not detected within 1.6 seconds the watchdog will time out and force the reset outputs active. ENDURANCE AND DATA RETENTION The SMS2916 is designed for applications requiring 1,000,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 1,000,000 erase/write cycles. Reset Controller Description The SMS2916 provides a precision RESET controller that ensures correct system operation during brown-out and power-up/-down conditions. It is configured with two open drain RESET outputs; pin 7 is an active high output and pin 2 is an active low output. During power-up, the RESET outputs remain active until VCC reaches the VTRIP threshold and will continue driving the outputs for approximately 200ms after reaching VTRIP. The RESET outputs will be valid so long as VCC is > 1.0V. During power-down, the RESET outputs will begin driving active when VCC falls below VTRIP. The RESET pins are I/Os; therefore, the SMS2916 can act as a signal conditioning circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset timeout after detecting a low to high transition and the RESET input will initiate a reset timeout after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a reset conditioning circuit. WATCHDOG TIMER OPERATION The SMS2916 has a watchdog timer with a nominal timeout period of 1.6 seconds. Whenever the watchdog times out it will generate a reset output on both RESET and RESET. There are two methods of clearing the watchdog timer; the first is through the use of software, and the second is by strobing the WDI input pin. Software Method The watchdog timer will clear to t0 whenever the SMS2916 issues an ACKnowledge. Therefore, the host system will need to issue a start condition, followed by a valid address and command. It can be a normal command as in the sequence of reading or writing to the memory, or it can be a dummy command issued solely for the purpose of resetting the watchdog timer. Refer to Figure 12 for detailed sequence of operations. The watchdog timer will be held in the cleared state during power-on while VCC is less than VTRIP. Once VCC exceeds VTRIP the watchdog will continue to be held in a cleared state for the duration of tPURST. After tPURST, the timer will be released and begin counting. If either reset input is asserted the watchdog timer will be cleared and remain in the reset condition until either tPURST has expired or the reset input is released, whichever is longer. If the watchdog times out and no action is taken by the host the SMS2916 will drive the reset outputs active for the duration of tPURST at which point it will release the outputs and clear the watchdog timer again and release it to begin a new count. Refer to Figure 13 for detailed sequence of operations. Hardware Method A high to low transition on WDI will clear the watchdog timer. If a transition is not detected within 1.6 seconds the watchdog will time out and force the reset outputs active. 2028-02 4/24/98 6 SMS2916 Preliminary SCL from Master Data Output from Transmitter Data Output from Receiver Start Condition 1 8 9 tAA tAA ACKnowledge 2028 ILL7.0 FIGURE 5. ACKNOWLEDGE RESPONSE FROM RECEIVER CHARACTERISTICS OF THE I2C BUS General Description The I2C bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are: a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus (See Figure 1). Data transfer between devices may be initiated with a START condition only when SCL and SDA are HIGH (bus is not busy). Input Data Protocol One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock HIGH time, because changes on the data line while SCL is HIGH will be interpreted as start or stop condition. START and STOP Conditions When both the data and clock lines are HIGH, the bus is said to be not busy. A HIGH-to-LOW transition on the data line, while the clock is HIGH, is defined as the "START" condition. A LOW-to-HIGH transition on the data line, while the clock is HIGH, is defined as the "STOP" condition . DEVICE OPERATION The SMS2916 is a 16K-bit serial E2PROM. The device supports the I2C bidirectional data transmission protocol. The protocol defines any device that sends data onto the bus as a "transmitter" and any device which receives data as a "receiver." The device controlling data transmission is called the "master" and the controlled device is called the "slave." In all cases, the SMS2916 will be a "slave" device, since it never initiates any data transfers. Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the master or the slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to ACKnowledge that it received the eight bits of data (See Figure 5). The SMS2916 will respond with an ACKnowledge after recognition of a START condition and its slave address byte. If both the device and a write operation are selected, the SMS2916 will respond with an ACKnowledge after the receipt of each subsequent 8-bit word. In the READ mode, the SMS2916 transmits eight bits of data, then releases the SDA line, and monitors the line for an ACKnowledge signal. If an ACKnowledge is detected, and no STOP condition is generated by the master, the SMS2916 will continue to transmit data. If an ACKnowledge is not detected, the SMS2916 will terminate further data transmissions and awaits a STOP condition before returning to the standby power mode. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see figure 6). For the SMS2916 this is fixed as 1010[B]. DEVICE IDENTIFIER 1 0 1 0 A 10 A 9 A 8 R/W 2028 ILL8.0 FIGURE 6. SLAVE ADDRESS BYTE 2028-02 4/24/98 7 SMS2916 Preliminary The next three bits are the high order address bit A8. Read/Write Bit The last bit of the data stream defines the operation to be performed. When set to "1," a read operation is selected; when set to "0," a write operation is selected. WRITE OPERATIONS The SMS2916 allows two types of write operations: byte write and page write. The byte write operation writes a single byte during the nonvolatile write period (tWR). The page write operation allows up to 16 bytes in the same page to be written during tWR. Byte WRITE Upon receipt of both the slave address and word address, the SMS2916 responds with an ACKnowledge for each. After receiving the next byte of data, it again responds with an ACKnowledge. The master then terminates the transfer by generating a STOP condition, at which time the SMS2916 begins the internal write cycle. While the internal write cycle is in progress, the SMS2916 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 7 for the address, ACKnowledge and data transfer sequence. Page WRITE The SMS2916 is capable of a 16-byte page write operation. It is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word, the master can transmit up to 15 more bytes of data. After the receipt of each byte, the SMS2916 will respond with an ACKnowledge. The SMS2916 automatically increments the address for subsequent data words. After the receipt of each word, the low order address bits are internally incremented by one. The high order five bits of the address byte remain constant. Should the master transmit more than 16 bytes, prior to generating the STOP condition, the address counter will "roll over," and the previously written data will be overwritten. As with the byte-write operation, all inputs are disabled during the internal write cycle. Refer to Figure 7 for the address, ACKnowledge and data transfer sequence. Acknowledges Transmitted from SMS2916 to Master Receiver If single byte-write only, Stop bit issued here. Acknowledges Transmitted from SMS2916 to Master Receiver SDA Bus Activity 1010 AAXR 10 9 W A C Word Address K AAAAAAAA 76543210 A C K Data Byte n A C K A Data Byte n+1 C K DDDDDDDD 76543210 Data Byte n+15 C K DDDDDDDD 76543210 A AA X 10 9 0 DDDDDDDD 76543210 S T Device Type A R Address Read/Write T 0= Write S T O P Slave Address Master Sends Read Request to Slave Master Writes Word Address to Slave Master Writes Data to Slave Master Writes Data to Slave Master Writes Data to Slave Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver 2028 ILL9.0 Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Shading Denotes SMS2916 SDA Output Active FIGURE 7. PAGE/BYTE WRITE MODE 2028-02 4/24/98 8 SMS2916 Preliminary Acknowledge Polling When the SMS2916 is performing an internal WRITE operation, it will ignore any new START conditions. Since the device will only return an acknowledge after it accepts the START, the part can be continuously queried until an acknowledge is issued, indicating that the internal WRITE cycle is complete. To poll the device, give it a START condition, followed by a slave address for a WRITE operation (See Figure 8). Internal WRITE Cycle In Progress; Begin ACK Polling READ OPERATIONS Read operations are initiated with the R/W bit of the identification field set to "1." There are four different read options: 1. 2. 3. 4. Current Address Byte Read Random Address Byte Read Current Address Sequential Read Random Address Sequential Read Issue Start Issue Slave Address and R/W = 0 Issue Stop Current Address Byte Read The SMS2916 contains an internal address counter which maintains the address of the last word accessed, incremented by one. If the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. When the SMS2916 receives the slave address field with the R/W bit set to "1," it issues an acknowledge and transmits the 8-bit word stored at address location n+1. The current address byte read operation only accesses a single byte of data. The master does not acknowledge the transfer, but does generate a stop condition. At this point, the SMS2916 discontinues data transmission. See Figure 9 for the address acknowledge and data transfer sequence. ACK Returned? No Yes (Internal WRITE Cycle is completed) Next operation a WRITE? Yes Issue Byte Address Issue Stop No Proceed with WRITE Await Next Command 2028 ILL10.0 FIGURE 8. ACKNOWLEDGE POLLING SDA Bus Activity 1 X XXR W A C K Data Byte 1010 S T Device Type A Address R T 1 DDDDDDDD 76543210 1 S T O P Read/Write 1= Read Slave Address Master sends Read request to Slave Lack of ACK (low) from Master determines last data byte to be read Slave sends Data to Master Slave Transmitter to Master Receiver Master Transmitter to Slave Receiver Shading Denotes SMS2916 SDA Output Active 2028 ILL11.0 FIGURE 9. CURRENT ADDRESS BYTE READ MODE 2028-02 4/24/98 9 SMS2916 Preliminary Random Address Byte Read Random address read operations allow the master to access any memory location in a random fashion. This operation involves a two-step process. First, the master issues a write command which includes the start condition and the slave address field (with the R/W bit set to WRITE) followed by the address of the word it is to read. This procedure sets the internal address counter of the SMS2916 to the desired address. After the word address acknowledge is received by the master, the master immediately reissues a start condition followed by another slave address field with the R/W bit set to READ. The SMS2916 will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. At this point, the master does not acknowledge the transmission but does generate the stop condition. The SMS2916 discontinues data transmission and reverts to its standby power mode. See Figure 10 for the address, acknowledge and data transfer sequence. SDA Bus Activity 1010 S T Device Type A Address R T AAXR 10 9 W A C K Word Address A C K XXXR W A C K Data Byte AA 10 9 X 0 A AA A AA 765 4 32 AA 10 1010 S T Device Type A Address R T 1 D DD DD DD D 7 65 43 21 0 1 S T O P Read/Write 0= Write Read/Write 1= Read Slave Address Master sends Read request to Slave Master Writes Word Address to Slave Slave Address Master Requests Data from Slave Lack of ACK (low) from Master determines last data byte to be read Slave sends Data to Master Master Transmitter to Slave Receiver Shading Denotes SMS2916 SDA Output Active Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver 2028 ILL12.0 FIGURE 10. RANDOM ADDRESS BYTE READ MODE 2028-02 4/24/98 10 SMS2916 Preliminary Sequential READ Sequential READs can be initiated as either a current address READ or random access READ. The first word is transmitted as with the other byte read modes (current address byte READ or random address byte READ); however, the master now responds with an ACKnowledge, indicating that it requires additional data from the SMS2916. The SMS2916 continues to output data for each ACKnowledge received. The master terminates the sequential READ operation by not responding with an ACKnowledge, and issues a STOP conditions. During a sequential read operation, the internal address counter is automatically incremented with each acknowledge signal. For read operations, all address bits are incremented, allowing the entire array to be read using a single read command. After a count of the last memory address, the address counter will `roll-over' and the memory will continue to output data. See Figure 11 for the address, acknowledge and data transfer sequence. Acknowledges from SMS2916 Acknowledge from Master Receiver Lack of Acknowledge from Master Receiver SDA Bus Activity AA R X 10 9 W A C Word Address K AAAAAAAA 76543210 A C K XX X R W A C K A First Data Byte C K DD DD DD DD 76 54 32 10 Last Data Byte 1 0 1 0 10 S T Device A Type R Address T AA 9X 0 1010 S T Device A Type R Address T 1 DD DD DD DD 76 54 32 10 1 S T O P Read/Write 0= Write Read/Write 1= Read Slave Address Master sends Read request to Slave Master Writes Word Address to Slave Slave Address Master Requests Data from Slave Slave sends Data to Master Lack of ACK (low) determines last data byte to be read Slave sends Data to Master Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Master Transmitter to Slave Receiver 2028 ILL13.0 Shading Denotes SMS2916 SDA Output Active FIGURE 11. SEQUENTIAL READ OPERATION (starting with a Random Address READ) 2028-02 4/24/98 11 SMS2916 Preliminary S T A R T1010x x x R W S T O P SCL and SDA Idle A C K ACK response from SMS2916 Resets The Watchdog Timer S T A R T1010x x x R W S T O P SCL and SDA Idle A C K S T A R T1010x x x R W S T O P tPURST A C K RESET t < 1.6sec t0 t0 t > 1.6sec t0 2028 ILL14.1 FIGURE 12. SEQUENCE ONE S T A R T1010x x x R W S T O P SCL and SDA Idle A C K Watchdog Timer t0 tPURST SCL and SDA Idle S T A R T1010x x x R W S T O P A C K No Affect On tPURST RESET t > 1.6sec t0 t > 1.6sec t0 2028 ILL15.0 FIGURE 13. SEQUENCE TWO 2028-02 4/24/98 12 SMS2916 Preliminary Frequently the supervisory circuit will be deployed on a PC board that provides a peripheral function to a system. Examples might be modem or network cards in a PC or a PCMCIA card in a laptop. In instances like this the peripheral card may have a requirement for a clean reset function to insure proper operation. The system may or may not provide a reset pulse of sufficient duration to clear the peripheral or to protect data stored in a nonvolatile memory. The I/O capability of the RESET pins can provide a solution. The system's reset signal to the peripheral can be fed into the SMS2916 and it in turn can clean up the signal and provide a known entity to the peripheral's circuits. The figure below shows the basic timing characteristics under the assumption the reset input is shorter in duration than tPURST. The same reset output affect can be attained by using the active high reset input. RESET Input RESET Output RESET Output t PURST 2028 ILL16.0 If you happen to be using one of the more common supervisory circuits like a 1232, you might consider reducing your component count such as illustrated below. +5VDC 8051 Family Part PBRST +5VDC 1232 Vcc ST TOL RST GND RST RST ALE From This To This VCC 24C16 SCL GND SDA I/O I/O 8051 Family Part ALE SMS2916 WDI RST RST SCL SDA RST I/O I/O 2028 ILL18.1 GND 2028-02 4/24/98 13 SMS2916 Preliminary 8 Pin PDIP (Type P) Package .375 (9.525) PIN 1 INDICATOR .250 (6.350) .300 (7.620) .070 (1.778) .0375 (0.952) .015 (.381) Min. SEATING PLANE .130 (3.302) .060 .005 (1.524) .127 TYP. .100 (2.54) TYP. .130 (3.302) .018 (.457) TYP. 5-7TYP. (4 PLCS) 0-15 .350 (8.89) .009 .002 (.229 .051) 8pn PDIP/P ILL.3 8 Pin SOIC (Type S) Package JEDEC (150 mil body width) .050 (1.27) TYP. .050 (1.270) TYP. 8 Places .157 (4.00) .150 (3.80) .275 (6.99) TYP. 1 .196 (5.00) .189 (4.80) .030 (.762) TYP. 8 Places FOOTPRINT .061 (1.75) .053 (1.35) .020 (.50) x45 .010 (.25) .0192 (.49) .0138 (.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .035 (.90) .016 (.40) .244 (6.20) .228 (5.80) 8pn JEDEC SOIC ILL.2 2028-02 4/24/98 14 SMS2916 Preliminary ORDERING INFORMATION SMS2916 P I -2.7 T Tape and Reel Option Blank = Bulk T = Tape & Reel Operating Voltage Range A = 4.5V to 5.5V VTRIP Min. @ 4.25V B = 4.5V to 5.5V VTRIP Min. @ 4.50V 2.7 = 2.7V to 5.5V VTRIP Min. @ 2.55V 2028 ILL17.0 Base Part Number Package P = 8 Lead PDIP S = 8 Lead 150mil SOIC Operating Temperature Range Blank = 0C to +70C I = -40C to +85C 2028-02 4/24/98 15 |
Price & Availability of SMS2916
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